1. Field of the Invention
The present invention relates to a detecting circuit. More specifically, the present invention relates to a detecting circuit for use in a circuit for synchronously detecting a chroma signal of a color television.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a portion of a chroma signal processing circuit of a color television receiver which constitutes the background of the present invention. A composite video signal input terminal 1 is connected to the inputs of a bandpass filter 2 and a synchronizing separating circuit 8. The output of the bandpass filter 2 is connected to the first input of a chroma amplifier 3. The output of the chroma amplifier 3 is connected to a first input of a chroma demodulator 4, to a chroma signal input terminal 11 of an automatic color control detecting circuit (hereinafter referred to as an ACC detecting circuit) 5 and to a first input of an automatic phase control detecting circuit (hereinafter referred to as an APC detecting circuit) 6. The output of the chroma demodulator 4 is connected to a chroma demodulated signal output terminal 10. On the other hand, the output of the synchronizing separating circuit 8 is connected to the input of a delay circuit 9. A first output of the delay circuit 9 is connected to a switching signal input terminal 13 of the ACC detecting circuit 5 and the second input of the APC detecting circuit 6. The second output of the delay circuit 9 is connected to a switching signal input terminal 14 of the ACC detecting circuit 5 and the fourth input of the APC detecting circuit 6. A sample and hold signal output terminal 38 of the ACC detecting circuit 5 is connected to the second input of the chroma amplifier 3. The output of the APC detecting circuit 6 is connected to the input of a voltage controlled oscillator 7. The first output of the voltage controlled oscillator 7 is connected to the second input of the above described chroma demodulator 4. The second output of the voltage controlled oscillator 7 is connected to a carrier wave input terminal 12 of the above described ACC detecting circuit 5. The third output of the voltage controlled oscillator 7 is connected to the third input of the above described APC detecting circuit 6.
Now an operation of the FIG. 1 diagram will be described. The composite video signal input terminal 1 receives a composite video signal, i.e. a signal compositely including a video signal, a chroma signal and a synchronizing signal. The composite video signal undergoes extraction of a chroma signal (a signal including a carrier color signal and a burst signal) by means of the bandpass filter 2 and the chroma signal is amplified by the chroma amplifier 3, whereupon the amplified chroma signal (a) is supplied to the chroma demodulator 4, the ACC detecting circuit 5 and the APC detecting circuit 6. On the other hand, the composite signal also undergoes separation of a horizontal synchronizing signal by means of the synchronizing separating circuit 8, whereupon the horizontal synchronizing signal is delayed by the delay circuit 9 so as to have the same timing as the above described burst signal and the same is supplied to the ACC detecting circuit and the APC detecting circuit as switching signals (c) and (d). The switching signals (c) and (d) are adapted to have the opposite polarities (see FIG. 3). The voltage controlled oscillator 7 provides a continuous carrier wave to the chroma demodulator 4, the ACC detecting circuit 5 and the APC detecting circuit 6. The APC detecting circuit 6 and the voltage controlled oscillator 7 form a phase-locked loop. More specifically, the APC detecting circuit 6 makes synchronous detection of only the burst signal based on the inputted chroma signal (a), the carrier wave and the switching signals (c) and (d) and the output thereof is supplied to the voltage controlled oscillator 7, such that the frequency and the phase of the carrier wave obtained from the voltage controlled oscillator 7 may be consistent with those of the burst signal. The ACC detecting circuit 5 provides synchronous detection of only the burst signal based on the inputted chroma signal (a), the carrier wave (b) and the switching signals (c) and (d), whereupon the output is sampled and held and the sampled and held signal (e) is supplied to the chroma amplifier 3. The chroma amplifier 3 performs an automatic color control such that the amplitude of the burst signal in the chroma signal (a) may be constant as a function of the sampled and held signal (e). The chroma demodulator 4 performs chroma demodulation based on the inputted chroma signal (a) and the carrier wave, thereby to provide a chroma demodulated signal.
Meanwhile, a detecting circuit as shown in FIG. 2 is used for the above described ACC detecting circuit 5 or the APC detecting circuit 6. FIG. 2 is a schematic diagram of a conventional detecting circuit. Now the FIG. 2 detecting circuit is described by taking an example in which the same is used for the ACC detecting circuit 5. Basically the circuit comprises a synchronous detecting circuit, a switching circuit and a sample and hold circuit. Transistors 15 to 19 and 22 constitute a synchronous detecting circuit. Transistors 20 and 21 constitute a switching circuit. Transistors 23 to 26 constitute a sample and hold circuit. The transistors 19 and 22 constitute a first differential amplifying circuit. More specifically, the base of the transistor 19 and the base of the transistor 22 are connected to the chroma signal input terminal 11. The emitter of the transistor 19 and the emitter of the transistor 22 are connected to the junction B, which is connected to the ground through a constant current source 29. The collector and the emitter of each of the transistors 19 and 22 are connected to the collector and the emitter of each of the switching transistors 20 and 21, respectively. The base of each of the transistors 20 and 21 is connected to the switching signal input terminal 13. The transistors 15 and 16 constitute a second differential amplifier and the transistors 17 and 18 constitute a third differential amplifier, such that the second and the third differential amplifiers may be connected in a dual balance type. More specifically, the base of the transistor 15 and the base of the transistor 16 are connected to the carrier wave input terminal 12. The emitter of the transistor 15 and the emitter of the transistor 16 are connected to the collector of the transistor 19. Similarly, the base of the transistor 17 and the base of the transistor 18 are connected to the carrier wave input terminal 12. The emitter of the transistor 17 and the emitter of the transistor 18 are connected to the collector of the transistor 22. The collector of the transistor 15 and the collector of the transistor 17 are connected to the voltage source input terminal 27. The collector of the transistor 16 and the collector of the transistor 18 are connected to the junction A, which is connected through a resistor 28 to a voltage source input terminal 27. The junction A constitutes a detected signal output. The junction A is connected to the base of the transistor 23. The collector of the transistor 23 is connected to the voltage source input terminal 27. The emitter of the transistor 23 is connected through a resistor 30 to the base of the transistor 24. The collector of the transistor 24 is connected to the voltage source input terminal 27. The emitter of the transistor 24 is connected through a resistor 33 to the sample and hold signal output terminal 38. A holding capacitor 34 is connected between the sample and hold signal output terminal 38 and the ground. The transistors 25 and 26 constitute a differential amplifier. The emitter of the transistor 25 and the emitter of the transistor 26 are connected through a constant current source 32 to the ground. The collector of the transistor 25 is connected to the base of the transistor 24. The base of the transistor 25 is connected to a bias voltage source 31. The collector of the transistor 26 is connected to the emitter of the transistor 24. The base of the transistor 24 is connected to the switching signal input terminal 14.
Now an operation of the FIG. 2 diagram will be described with reference to FIG. 3. FIG. 3 is a graph showing waveforms of the signals at various portions of the FIG. 2 diagram. The chroma signal input terminal 11 receives the above described chroma signal (a). The chroma signal (a) includes a carrier color signal a.sub.1 and a burst signal a.sub.2. The carrier wave input terminal 12 receives the above described carrier wave (b), not shown. The switching signal input terminal 13 receives the above described switching signal (c). The switching signal (c) assumes the low level during a period in which the burst signal a.sub.2 is obtained (referred to as a burst signal period hereinafter), and assumes the high level during the remaining period. Conversely, the above described switching signal (d) assumes the high level during the burst signal period and assumes the low level during the remaining period. The transistors 20 and 21 are turned off only during the burst signal period as a function of the switching signal (c). Accordingly, the transistors 19 and 22 operate as a detector only during the burst signal period and therefore a product of the carrier wave (b) supplied to the carrier wave input terminal 12 and the burst signal a.sub.2 is evaluated, whereby the burst signal a.sub.2 is synchronously detected and the output is obtained as a burst signal a.sub.2 ' at the junction A. The signal obtained at the junction A is supplied to the transistor 23 and the same is sampled only during the burst signal period as a function of the switching signal (d) while the same is held during the non-burst signal period, whereupon the above described sampled and held signal (e) is obtained at the sample and hold signal output terminal 38.
Now the potential V.sub.A at the junction A will be described. Let it be assumed that the source voltage applied to the voltage source input terminal 27 is V.sub.cc, the current value of the constant current source 29 is I.sub.0, and the resistance value of the resistor 28 is R. First the direct current voltage V.sub.0 of the potential V.sub.A at the junction A in the absence of the chroma signal will be described. Since the switching signal (c) assumes the high level during the non-burst signal period, the transistors 20 and 21 are turned on and accordingly the transistors 19 and 22 are short-circuited, whereby the circuit does not perform a detecting operation and hence the current I.sub.0 of the constant current source 29 flows equally into the transistors 20 and 21 as I.sub.0 /2 for each, in which case the current I.sub.0 /2 flowing through one flows through the resistor 28 and the current I.sub.0 /2 flowing through the other flows directly from the voltage source. Accordingly, the direct current potential V.sub.0 becomes as follows: EQU V.sub.0 =V.sub.cc -R.multidot.I.sub.0 /2 (1)
Since the switching signal (c) assumes the low level during the burst signal period, the transistors 20 and 21 are turned off. Accordingly, the circuit performs the detecting operation. However, since the current I.sub.0 of the constant current source 29 flows equally through the transistors 19 and 22 as I.sub.0 /2 for each, the direct current potential V.sub.0 becomes as follows as described previously: EQU V.sub.0 =V.sub.cc -R.multidot.I.sub.0 /2 (2)
Accordingly, the direct current potential V.sub.0 is not changed even by the level change of the switching signal (c). Now in the presence of the chroma signal, the burst signal is detected as described previously during the burst signal period and therefore the potential V.sub.A at the junction A becomes the direct current potential V.sub.0 superimposed on the burst signal a.sub.2 '.
As described in the foregoing, in the conventional detecting circuit, two transistors, i.e. the transistors 20 and 21 were required as a switching means for performing a detecting operation only during the burst signal period. Furthermore, although the detected signal is normally sampled and held, in the conventional detecting circuit the direct current potential V.sub.0 out of the potential V.sub.A at the junction A is not changed for the burst signal period and the non-burst signal period, as described previously, and therefore the sample and hold circuit becomes complicated. More specifically, referring to FIG. 2, the sample and hold circuit 39 requires the buffer transistor 23 and the resistor 30 as a means for providing a changing voltage for cutting off the transistor 24 during the non-burst signal period. Although such detecting circuit has been incorporated recently in an integrated circuit, it is desired that the number of devices can be decreased and hence the scale of integration can be decreased as much as possible in view of a recent increasing scale of integration of such integrated circuits.